The present invention relates generally to adjusting the supply voltage applied to an integrated circuit (IC).
Integrated circuits (ICs) typically include many switching elements, such as transistors. These switching elements are configured to perform a variety of circuit functions.
The operation of a transistor is typically affected by its process, voltage, and temperature (“PVT”). The “process” component of PVT refers to the process of manufacturing a transistor. The process is often classified as “fast”, “slow”, “nominal”, or anywhere in between. Roughly speaking, a transistor manufactured using a fast process will transmit signals at a faster rate as compared to a transistor manufactured using a slower process. Likewise, a transistor manufactured using a slow process will, roughly speaking, transmit signals at a slower rate as compared to a transistor manufactured using a faster process. Once a transistor is manufactured using a particular process, the effect of the process is fixed. Thus, the “process” component of PVT cannot be adjusted to change the operating characteristics of a manufactured transistor.
The “temperature” component of PVT is the temperature at which the transistor operates. Similar to the process used to manufacture a transistor, the temperature at which a transistor operates affects how a transistor operates. In particular, the rate at which a transistor transmits a signal is affected by the temperature at which the transistor operates. For example, a transistor operating at a reference temperature requires a higher voltage to transmit signals at a higher rate. If the temperature of the transistor decreases, less voltage is needed to transmit signals at that rate. Similarly, if the temperature of the transistor increases, more voltage is needed to transmit signals at the higher rate. The “temperature” component of PVT varies during operation of the transistor. While there is some control over the temperature of an IC, such temperature cannot be sufficiently adjusted to result in a change in its operating characteristics.
The only component of PVT that can be varied effectively during operation to adjust a transistor's characteristics is its voltage. The optimum supply voltage of a transistor varies depending on the transistor's process (e.g., fast or slow) and the transistor's operating temperature. A conventional solution to the variation in the optimum supply voltage is to set the supply voltage to a worst-case value. In transistors manufactured with a fast process or operating at a low temperature, this conventional solution often results in too much power being supplied to a transistor, with the excess power being dissipated.
As an example, if a circuit designer determines (e.g., via simulation of an IC having many transistors) that a transistor manufactured with a slow process needs 3.2 V as a supply voltage, the circuit designer may provide a supply voltage of 3.2 V to each transistor on the IC. If another transistor on the IC was manufactured with a fast process, however, that transistor may only need a supply voltage of 3.0 V. When 3.2 V is supplied, excess power is dissipated on the transistor that only needs 3.0 V as a supply voltage. As the number of transistors on the IC that were manufactured with a fast process (or are operating at a low temperature) increases, the amount of dissipated power increases.
There have been several prior art techniques used to adjust the voltage supplied to transistors on an IC so as to reduce the amount of dissipated power. FIG. 1 shows one prior art technique—a prior art phase lock loop (PLL) oscillator 100. The PLL oscillator 100 adjusts the supply voltage by measuring a time delay between the input reference clock and output clock from a row of inverters 105. Thus, the PLL oscillator 100 uses the time domain to adjust the supply voltage.
In more detail, when a digital “1” is transmitted to the first inverter 110, the first inverter 110 outputs a digital “0”, which is then transmitted to a second inverter 115. This process continues through the row of inverters 105 until a digital “1” is outputted from a sixth inverter 120. Thus, the output is the same as the input (i.e., a digital “1”) but is delayed due to the propagation of the input through the row of inverters 105.
The input 123 to the row of inverters 105 is an analog signal (i.e., a sine wave). Input 123 and output 125 of the row of inverters 105 are both transmitted to a phase detector 130. The phase detector 130 determines whether the voltage phase of an input sine wave at input 123 is phase aligned with the voltage phase of an output sine wave at output 125. In particular, the phase detector 130 detects whether the phase of the output signal at output 125 leads or lags the phase of the input signal at input 123. If the sine waves are not phase aligned, charge pump 133 charges or discharges for phase difference and adjusts voltage source 135, which in turn changes the supply voltage applied to each inverter in the row of inverters 105. As the voltage applied to the row of inverters changes, the delay that each inverter introduces to the input signal at input 123 will change. As a result, the phase of the output signal (sine wave) at output 125 is adjusted. The changing of the voltage supplied to each inverter in the row of inverters 105 stops when the phase of the input signal at input 123 and the phase of the output signal at output 125 are aligned.
FIG. 2 is a block diagram of another prior art circuit 200 that uses the time domain to adjust the voltage supplied to transistors on an IC so as to reduce the amount of dissipated power. An input signal 205a is transmitted to input 205 of a buffer 210. The buffer 210 delays the signal to produce an output signal 215a on output line 215. The output signal 215a is transmitted to an exclusive OR (XOR) gate 220. The XOR gate 220 produces an XOR signal 225a on signal line 225. XOR signal 225a represents the time delay between the output signal 215a and the input signal 205a. 
The signal 225a is then input to a filter 230 for filtering and then to an analog-to-digital converter (ADC) 235 to convert the analog signal to a digital signal. The digital signal is then transmitted to a comparator 240 which compares the digital bits to a target PVT code 245. The target PVT code 245 is a code that represents a target signal for the voltage supplied to the buffer 210. The comparator 240 is used to control the voltage of the buffer 210 (via a feedback loop 250) (e.g., by increasing or decreasing the buffer voltage) based on its comparison with the target PVT code 245.
There are several problems associated with these prior art solutions. As described above, when setting the supply voltage to a worst case value, significant power is dissipated. Also, when using the time domain to determine the time delay and to adjust the supply voltage based on this time delay, the measured delay may be inaccurate due to jitter (i.e., the unwanted variation of one or more signal characteristics). Further, circuitry specific to determining the time delay is often needed in the IC to adjust the supply voltage.
Therefore, there is a need for an improved technique for adjusting the supply voltage applied to switching elements in a circuit.